Technical Field
The invention relates in general to a booting method of a main chip.
Background
In a general booting process utilizing a NAND Flash, configuration of the NAND Flash, including page size, block size and a error correction code (ECC) type, has to be shown to a main chip, so that the main chip can initialize the NAND Flash and then send instructions to read the NAND Flash.
Traditionally, the configuration information of the NAND Flash is obtained in two ways. In the first way, 5 general purpose I/O (GPIO) pins of the main chip are utilized to connect to the NAND Flash to obtain the configuration information. Two of the GPIO pins are utilized to obtain information of the page size, another two of the GPIO pins are utilized to obtain information of the block size, and the remain one of the GPIO pins is utilized to obtain information of the ECC type. Then, the main chip is able to initialize the NAND Flash according to the configuration information obtained by the GPIO pins. However, utilization of the GPIO pins makes the cost of package remain high.
In the second way, a boot table including identifications (IDs) of the current NAND Flashes and corresponding configuration information may be created, and then recorded in a read only memory (ROM). When the NAND Flash is utilized to boot, the main chip may read the ID form the NAND Flash and then look it up in the boot table in the ROM accordingly, so as to obtain the corresponding configuration information. Afterwards, the main chip can initialize the NAND Flash according to the configuration information obtained from the boot table. However, the boot table only records existing NAND Flashes, thus lack of expandability and unable to support the future new NAND Flashes.